Synopsys Design Compiler Tutorial 2021 Online

write -format verilog -hierarchy -output $db_dir/$DESIGN_NAME_netlist.v

report_area -hierarchy > reports/area.rpt synopsys design compiler tutorial 2021

After reading, check for generic mapping: reports/area.rpt After reading

This critical file tells DC where to find libraries. Key variables include: search_path : Directories for RTL and libraries. synopsys design compiler tutorial 2021

# Define the link library (used to resolve references) set link_library [list * slow.db]

write_sdc constraints/my_design.sdc